As used herein, the term "high voltage" refers to voltages of nominally 5 volts or more; the term "low voltage" refers to voltages significantly less than 5 volts, being typically 3.3 volts or less. The term "high voltage transistor" refers to a transistor designed to operate with a minimum of degradation at a high voltage (e.g., a thick-oxide transistor); and the term "low voltage transistor" refers to a transistor designed to operate only at a low voltage (e.g., a low-voltage CMOS transistor).
The use of embedded flash Electronically Erasable Programmable Read Only (EEPROM) memory in cellular phones, answering machines, cordless phones and other silicon integrated circuits is increasing. Current generation flash EEPROMS require the use of circuitry and thick-oxide transistors capable of handling relatively high voltages (e.g., 5 volts and higher, typically 7 volts) for erasing and programming (writing) flash memory. These high voltage transistors are needed in the critical read column precharge path of these prior art EEPROM's because the columns must be raised to high voltages during erase and programming operations. There are drawbacks, however, to using high voltage transistors in EEPROM's; high voltage transistors operated at high voltages are subject to parameter degradation and are inherently less reliable than low voltage core CMOS transistors operated at lower voltages (e.g., less than 5 volts, typically about 3 volts or less). Thus the characteristics of high voltage transistors cannot be relied upon for successful read mode operation. Read precharge and cycle times are also increased when high voltage transistors are used in the critical read column precharge path because of their significantly lower gain (typically less than one-half the gain of low voltage core CMOS transistors).
FIG. 1 illustrates a prior art EEPROM circuit 10. In FIG. 1 a flash EEPROM memory array 20 is shown having N columns (C.sub.1, C.sub.2, . . . C.sub.N) and M rows (R.sub.1, R.sub.2, . . . R.sub.M) and an associated on-pitch sense amplifier block 30, column select transistor block 40, high voltage column precharge transistor block 50, and write/erase data transfer gate block 60. The column precharge transistor block 50 comprises thick oxide, high voltage transistors 51(1), 51(2) . . . , 51(N). They must be high voltage, thick-oxide transistors to protect their gate oxides when high voltage is applied to their drains along columns C.sub.1 C.sub.2, and C.sub.N during erase and write operations.
As is known in the art, when erasing a flash EEPROM memory array, all columns must be raised to a high voltage, typically 7 volts, and the rows, R.sub.1, R.sub.2, . . . , R.sub.M, kept at ground (0 volts) or reduced to a negative potential below ground. When writing a flash EEPROM memory array 20, columns associated with cells to be written are also raised to a high potential, typically 7 volts, as is the row associated with the cells to be written to. Other columns associated with cells along the same row and not to be written to remain at ground. When erasing or writing, it is therefore necessary to raise one or more columns to high voltage levels and the transistors associated with the column precharge transistor block must be high-voltage thick oxide transistors.
With reference to the first column C.sub.1 in FIG. 1, the method and circuitry of the prior art will be described. In preparation for applying high voltage to the first column C.sub.1 a high voltage, typically 7 volts, is applied to the data input D.sub.1 and the read control input RC.sub.1 of the write/erase data transfer gate block 60. This sets up the data but blocks conduction through devices M7 and M8. The high voltage is transferred onto column C1, initiating the write or erase, by lowering the read control input RC.sub.1, This turns on devices M7 and M8 passing the high voltage from data input D.sub.1 onto the column. Prior to applying high voltage to these inputs (D.sub.1 and RC.sub.1), the precharge input must be set to ground to prevent conduction through the precharge transistor 51(1) within precharge block 50.
For those columns associated with cells not to be written but along the same row as other cells being written, their voltage is kept at ground by keeping their data inputs (i.e., D.sub.1, D.sub.2, . . . D.sub.N) at ground.
The column select transistor block 40 and sense amplifier block 30 are used for reading the flash memory. Care must be taken not to over-voltage stress the transistors in these blocks during write or erase. If column select transistors 41(1), 41(2) . . . 41(N) in column select block 40 are low voltage transistors, their gates (COLEN input 42) must be set to VDD level (e.g. 3 volts) prior to raising the column voltage above VDD; otherwise the gate-to-drain voltage will go to a high voltage and possibly damage the transistor's gate oxide. With their gates at VDD and the columns raised high, the inputs to the sense amplifiers(s) (N.sub.1, N.sub.2 . . . , N.sub.n) will be VDD-Vt. This will not over-stress any transistors in the sense amplifier. Alternatively, the column select transistors 41(1), 41(2) . . . 41(N) in the column select transistor block 40 could be high voltage transistors. In this case COLEN input 42 can be set at ground, blocking conduction through these devices.
During erase and write operations the gates of precharge transistors 51(1), 51(2), . . . 51(N) are at ground (0 volts) along PRECHARGE input 52. This results in a high gate-to-drain potential (e.g., 7 volts) for each transistor, which is easily withstood by the high voltage transistors (but which would destroy low voltage core CMOS transistors). However, due to their low gain, use of high voltage transistors in the precharge path limits circuit performance by increasing precharge and cycle time. The characteristics of high voltage transistors also degrade over time when operated at high voltages. This degradation may lengthen precharge time during read operations.
As is well known, the write/erase data inputs D.sub.1, D.sub.2, . . . D.sub.N and the read control signal input RC.sub.1 of write/erase data transfer gate block 60 must be at high voltage levels when asserted to carry out the write or erase functions. Thus, off-pitch circuitry (not shown) needed to generate these signals must also include high voltage transistors. Because high voltage transistors are generally less reliable than low voltage transistors, this increased use of high voltage transistors may lead to a less reliable EEPROM.